Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

PLL Issues

Hi, In my code, I need to do 10MHz to 50MHz PLL and transfer the output to about 10 internal modules. Is it customary and synthesizable? Is there any restriction for Altera PLL fun out Can...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

for jitter I assume the tool may report the achieved value. so I don't know for sure, just a guess.

With dc fifo you certainly got an issue to look at as possible reason especially if your timing slack at fifo was too small to begin with.