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Honored Contributor
Honored ContributorPLL Issues
Hi, In my code, I need to do 10MHz to 50MHz PLL and transfer the output to about 10 internal modules. Is it customary and synthesizable? Is there any restriction for Altera PLL fun out Can...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Why for ALTPLL if clock multiplication factor =1 and clock division factor =1, then timings are met. But if I change: multiplication factor =9 and clock division factor =10, then the timings ( of the schematic, that follows ALTPLL ) are not met although the resulting clock is even lower, then the original. P.S. SDC file contains: derive_pll_clocks derive_clock_uncertainty --- Quote End --- just a guess. It could be that clock jitter gets more such that it becomes in effect higher than first case. Or it could be your design has multiple clock domains. or it is bad marginal design coincidence.
