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Altera_Forum
Honored Contributor
Honored ContributorPLL Issues
Hi, In my code, I need to do 10MHz to 50MHz PLL and transfer the output to about 10 internal modules. Is it customary and synthesizable? Is there any restriction for Altera PLL fun out Can...
Altera_ForumHonored Contributor
Honored ContributorTransfers between clocks with non-integer factors are hard (or virtually impossible) to meet timing.
If you think about the possible clock edges of those two clocks, you'll see that some inevitably,< sometimes the edges will be damn close together. For such cases, when the tools can't ensure the timing is met, the usual method is to handle them as asynchronous and live with the possible cases of metastability. (Use a DCFIFO with 2 or more stages). That said, ou just wanted a 10 MHz and a 50 MHz clock. Hoyw come you ended up having a 9/10 factor?
