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Altera_Forum's avatar
Altera_Forum
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14 years ago

PLL issues in EP3C16

I'm sure I'm missing something simple here. I have a VHDL state machine that is running from a 50MHz input clock, and I want to boost that to 100MHz using a PLL. Either the PLL is not locking or I screwed something else up, because though everything compiles fine, I get no output from my state machine, even if I change the PLL to just give me a 1-to-1 of the input clock (50MHz). I've tried every different compensation scheme, with no luck.

Any ideas?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    As you said, it's supposed to work if setup correctly.

    PLL lock state can be checked by monitoring the lock output, e.g. by sending it to a pin or SignalTap.

    I presume, that you don't have e.g. unconnected reset signals to the PLL.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If you can validate you are not receiving a Lock signal, check the VCCA inputs (should be 2.5V).

    I know the PLL's are sensitive to ripple on this supply, But My typical experience was it would still lock most of the time, but occasionally would loose lock or take longer to lock than expected.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    sorry I'm just getting back around to working on this issue...

    thanks very much for those suggestions -- the VCCA supply could very possibly be the issue. Though the VCCA pins are properly decoupled and connected to my 2.5V supply through a ferrite, the 2.5V is also supplying BLVDS i/o pins and the supply runs a little hot. I'm going to try some things on this front and post my findings.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Well I got dragged away from this problem again for a couple of weeks, and just got back on it yesterday, and quickly found the problem. Somehow the GNDA pins on the FPGA were left floating in my schematic, and we never caught it. Fortunately, I had 100% of the BGA pins routed to vias (sweet forethought), as well as soldermask voids on the bottom layer vias, so I was able to make a delicate mod to tie these pins to ground, and everything is happy. Thanks to everyone for their help!