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Altera_Forum
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15 years ago

PLL issues in EP3C16

I'm sure I'm missing something simple here. I have a VHDL state machine that is running from a 50MHz input clock, and I want to boost that to 100MHz using a PLL. Either the PLL is not locking or I ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Well I got dragged away from this problem again for a couple of weeks, and just got back on it yesterday, and quickly found the problem. Somehow the GNDA pins on the FPGA were left floating in my schematic, and we never caught it. Fortunately, I had 100% of the BGA pins routed to vias (sweet forethought), as well as soldermask voids on the bottom layer vias, so I was able to make a delicate mod to tie these pins to ground, and everything is happy. Thanks to everyone for their help!