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Honored Contributor
Honored ContributorPLL issues in EP3C16
I'm sure I'm missing something simple here. I have a VHDL state machine that is running from a 50MHz input clock, and I want to boost that to 100MHz using a PLL. Either the PLL is not locking or I ...
Altera_ForumHonored Contributor
Honored ContributorAs you said, it's supposed to work if setup correctly.
PLL lock state can be checked by monitoring the lock output, e.g. by sending it to a pin or SignalTap. I presume, that you don't have e.g. unconnected reset signals to the PLL.
