PLL clock input freq range

if you're out of that range, your pll could lose lock.

In Practical cases ,

You may get a lock on a few devices because the range has some guard band. THis is not guaranteed for every device or across temperature.

PLL will lose lock if the clock edge mis-alignment between the input clock and the feedback clock exceed the lock window. The lock window can be calculated. It may also be reported in the PLL settings in the report file generated by QII. So, it can lose lock if the frequency is too far away from the actual specified frequency. How much is too far, well you have to exceed the lock range for each frequency setting. Data may be available in characterization reports by contacting Altera. Also, you may lose lock if the clock uncertainty (function of jitter components) exceeds the lock window.

Hi Justin ,

You're welcome. There are roughly 16,000 different PLL settings so I would suggest to try different settings. I can help you manually pick settings to see if we can do better than what Quartus II is choosing. I'll need to know your PLL requirements and settings that you entered into Quartus II.

First we'll see if one setting will cover the range you desire. If not we will need to use multiple settings and PLL reconfiguration as FPGA_Guy suggested earlier.

I see , I know very little about PLL reconfiguration

Here: http://www.altera.com/literature/lit-stx2.jsp