PLL clock input freq range

PLL will lose lock if the clock edge mis-alignment between the input clock and the feedback clock exceed the lock window. The lock window can be calculated. It may also be reported in the PLL settings in the report file generated by QII. So, it can lose lock if the frequency is too far away from the actual specified frequency. How much is too far, well you have to exceed the lock range for each frequency setting. Data may be available in characterization reports by contacting Altera. Also, you may lose lock if the clock uncertainty (function of jitter components) exceeds the lock window.