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Altera_Forum
Honored Contributor
Honored ContributorPLL clock input freq range
Hi All , I have a question about PLL clock input freq range In the Fitter report , we can see the suggested range of Input Freq What will happen if the actual input frequency is out of that...
Altera_ForumHonored Contributor
Honored ContributorFirst we'll see if one setting will cover the range you desire. If not we will need to use multiple settings and PLL reconfiguration as FPGA_Guy suggested earlier.
