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Honored ContributorPLL clock input freq range
Hi All , I have a question about PLL clock input freq range In the Fitter report , we can see the suggested range of Input Freq What will happen if the actual input frequency is out of that...
Altera_ForumHonored Contributor
Honored Contributor Look for AN367: implementing PLL reconfiguration in Stratix II devices I learn about the PLL reconfiguration from this document. It is very useful.
