Occasional Contributorplacement of GPIO with ALTLVDS LVDS pins on same bank failed
Hello
- I am using Agilex7 , and I implemented the following LVDS design recommended by altera spec to place ALTLVDS and ALTLVDS RX on the same bank - (the bank used is 2F )
The design compiles and fit well on the FPGA , and the IO standard used for the LVDS RX and TX is : I/O standard True Differential Signaling
- next step I did , is to add some single ended GPIO for external control
I need the GPIO be on the same bank (2F) as the ALTLVDS RX and ALTLVDS TX pins
But the placement failed and this is the error message
Error(11924): Bank '2F' has conflicting VCCIO settings
Error(11928): 'TX_LVDS_ADC_4P~pad' with I/O standard True Differential Signaling, was constrained to be within bank '2F'
Info(11929): '1.5V' is a valid VCCIO value
Error(11928): 'GPIO1~pad' with I/O standard 1.2 V, was constrained to be within bank '2F'
Info(11929): '1.2V' is a valid VCCIO value
Seems some mismatch on the IO standard ...
Is there some way to place GPIO and ALTLVDS lanes correctly on the same bank ?
THX
Kikoss
Hello,
Unfortunately, for Agilex 7 devices, you cannot use single ended I/O in the bank that are using 1.5V for bank VCCIO. For VCCIO_PIO=1.5V, we don't support a single ended buffer, you can only configure the I/O for True Differential Signaling (TDS).
For VCCIO_PIO=1.2V, you can mix TDS RX and single ended 1.2V LVCMOS, 1.2V SSTL, etc in the same bank. We do not support TDS TX when VCCIO_PIO is 1.2V.
Reference:
TDS specification: https://www.intel.com/content/www/us/en/docs/programmable/683301/current/differential-i-o-standards-specifications.html
Single Ended I/O specification:
