Forum Discussion
Occasional Contributorplacement of GPIO with ALTLVDS LVDS pins on same bank failed
Hello,
Unfortunately, for Agilex 7 devices, you cannot use single ended I/O in the bank that are using 1.5V for bank VCCIO. For VCCIO_PIO=1.5V, we don't support a single ended buffer, you can only configure the I/O for True Differential Signaling (TDS).
For VCCIO_PIO=1.2V, you can mix TDS RX and single ended 1.2V LVCMOS, 1.2V SSTL, etc in the same bank. We do not support TDS TX when VCCIO_PIO is 1.2V.
Reference:
TDS specification: https://www.intel.com/content/www/us/en/docs/programmable/683301/current/differential-i-o-standards-specifications.html
Single Ended I/O specification:
Occasional ContributorI have no special requirement for the GPIO since it connected to a custom board that we develop and we can adjust the voltage following the FPGA possibilities
- I tried to set the GPIO to be 1.5V but the fiitter failed (this is my qsf command : set_instance_assignment -name IO_STANDARD "1.5 V" -to GPIO1 -entity safety_top_level)
- It failed also when I tried also to make the bank 1.5V as the following : set_global_assignment -name IOBANK_VCCIO 1.5V -section_id 2F
the error from the fitter is the same in the 2 cases
Error(12341): The output pin GPIO1 has a 1.5 V I/O standard, but the selected device does not support output pin operation with a 1.5 V I/O standard.
THX
