Forum Discussion
Occasional Contributorplacement of GPIO with ALTLVDS LVDS pins on same bank failed
Hello,
Unfortunately, for Agilex 7 devices, you cannot use single ended I/O in the bank that are using 1.5V for bank VCCIO. For VCCIO_PIO=1.5V, we don't support a single ended buffer, you can only configure the I/O for True Differential Signaling (TDS).
For VCCIO_PIO=1.2V, you can mix TDS RX and single ended 1.2V LVCMOS, 1.2V SSTL, etc in the same bank. We do not support TDS TX when VCCIO_PIO is 1.2V.
Reference:
TDS specification: https://www.intel.com/content/www/us/en/docs/programmable/683301/current/differential-i-o-standards-specifications.html
Single Ended I/O specification:
Super ContributorHi,
thanks fo your confidence. Unfortunately I'm not yet familiar with Agilex FPGA series.
As far as I understand Agilex 7 datasheet, true differential TX on GPIO banks requires VCCIO of 1.5 V, there's apparently no fitting single ended IO standard that could be used on an 1.5 V GPIO bank. What are your voltage requirements for single ended GPIO pin?
