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Altera_Forum
Honored Contributor
Honored ContributorPin Planner: Can't edit the current device because the device is read-only
Hello,
Under QuartusII, V12, Pin Planner, I can't plan any pins (modify pin location). error=Can't edit the current device because the device is read-only". Each time I compile the design the .pin file is overwritten so editing the .pin file is not an option. Under QuartusII>Projects>Add/remove_files_in_project>settings, I see no applicable setting. Online Altera guidance for the Pin Planner targets some old tool so nothing stated matches what I see in the QuartusII V12 Pin Planner. Does anyone know a way to bypass the pin planner and edit a file to map my FPGA pin functions as currently wired on my PCB? (I've lodged an SR 10870876 and will share any resulting wisdom) Thanks.4 Replies
Altera_Forum--- Quote Start --- Does anyone know a way to bypass the pin planner and edit a file to map my FPGA pin functions as currently wired on my PCB? --- Quote End --- I can't comment on your pin planner issues, as I never use it. Here's examples with Tcl scripts that perform pin assignments. http://www.alteraforum.com/forum/showthread.php?t=35687 http://www.alteraforum.com/forum/showthread.php?t=33462 http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial Cheers, Dave- Altera_Forum
Dave,
Thanks, I right away learnt two things from your post a) Search on "pin assignment: not "pin planner" b) Tcl is the way to go. I'm not quite there but I'm close: Tcl prompt....QuartusII>View>Utility_windows>Tcl_console Tcl script.....>source myscript.tcl After running myscript.tcl and compiling my VHDL I can see a) Under QuartusII>Assignment_editor that all my pin locations were accepted correctly and without complaint. b) Under Pin Planner I see every pin assignment in the assignment editor was ignored. ---snippet---------# QuartusII>View>Utilty_windows>tcl_console# >source maestro_pin.tcl# set_global_assignment -name family CYCLONE V# set_global_assignment -name device 5CGXFC7C7F23C8 set_location_assignment -to PIN_b12 debug_spi_sclk_0 set_location_assignment -to PIN_f12 debug_spi_syn_n_0 set_location_assignment -to PIN_c18 fpga_usb_uart_cts etc... ---end snippet--------- Some things that don't work... 1. despite Altera documentation of the tcl console saying otherwise >quartus_sh -t myfile.tcl does not work 2. the .qsf file QuickScriptEditor...no hits when search its help for "Pin" or "assignment". Search on "the" was sucessful :). Conclusion=.qsf files editor won't help me. - Altera_Forum--- Quote Start --- b) Tcl is the way to go. --- Quote End --- Most definitely. --- Quote Start --- I'm not quite there but I'm close: Tcl prompt....QuartusII>View>Utility_windows>Tcl_console Tcl script.....>source myscript.tcl After running myscript.tcl and compiling my VHDL I can see a) Under QuartusII>Assignment_editor that all my pin locations were accepted correctly and without complaint. b) Under Pin Planner I see every pin assignment in the assignment editor was ignored. --- Quote End --- Did you synthesize the design after applying the constraints? I'm not sure that the GUI windows mean anything until Quartus has had a chance to apply the settings to your design. --- Quote Start --- Some things that don't work... 1. despite Altera documentation of the tcl console saying otherwise >quartus_sh -t myfile.tcl does not work --- Quote End --- In what way? I've used it in the past and it works. You have to have your Tcl script create or open a project, and then you can create assignments that ultimately go in the .qsf file for the project. However, you can consider that .qsf file a 'generated' file and delete it at any time, since your Tcl script will regenerate it. Try running one of the synth.tcl scripts I created using quartus_sh. If it doesn't work, let me know and I'll fix it so that it works, and then you can use that as your reference script. Cheers, Dave
- Altera_Forum
Pin Planner assignment Problem solved...
a) Realization: Pin Planner is nothing more than a viewer for end results. b) The correct format of the Tcl, despite the example from [Tcl_Console]>help -examples is as follows. (PIN_name followed by SIGNAL_name) -----snippet------------# QuartusII>View>Utilty_windows>tcl_console# >source maestro_pin.tcl# Assignment Editor will show# To AssignmentName Value Enabled# debug_spi_sclk_0 Location PIN_B12 Yes set_location_assignment -to PIN_b12 debug_spi_sclk_0 set_location_assignment -to PIN_f12 debug_spi_syn_n_0 set_location_assignment -to PIN_c18 fpga_usb_uart_cts . . export_assignments -----end snippet---------- Notes: 1. The Assignment editor shows a check mark on each row no matter what nonsense text the Tcl script enters. 2. QuartusII>Project>Generate_Tcl_file_for_project is handy to capture any manual mods made in Assignment Editor.
