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b) Tcl is the way to go.
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Most definitely.
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I'm not quite there but I'm close:
Tcl prompt....QuartusII>View>Utility_windows>Tcl_console
Tcl script.....>source myscript.tcl
After running myscript.tcl and compiling my VHDL I can see
a) Under QuartusII>Assignment_editor that all my pin locations were accepted correctly and without complaint.
b) Under Pin Planner I see every pin assignment in the assignment editor was
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Did you synthesize the design after applying the constraints?
I'm not sure that the GUI windows mean anything until Quartus has had a chance to apply the settings to your design.
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Some things that don't work...
1. despite Altera documentation of the tcl console saying otherwise
>quartus_sh -t myfile.tcl
does not work
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In what way? I've used it in the past and it works.
You have to have your Tcl script create or open a project, and then you can create assignments that ultimately go in the .qsf file for the project. However, you can consider that .qsf file a 'generated' file and delete it at any time, since your Tcl script will regenerate it.
Try running one of the synth.tcl scripts I created using quartus_sh. If it doesn't work, let me know and I'll fix it so that it works, and then you can use that as your reference script.
Cheers,
Dave
Honored Contributor
