Agilex 7M HBM Bus Width Converter Failure

While testing an HBM DMA design we found our DMA read was seeing the data from the HBM, but words were missing.  We intended to read 36x 256-bit words.  We are seeing 18 words read and 18 words beyond the end of the expected address range.  Looking closer, we are seeing word 0, 3, 4, 7, 8 etc. so skipping 2 every 4 256-bit words. We suspect an issue between the 512-bit fabric NOC and the 256-bit AXI initiator.

It looks like platform designer just has a huge limitation regarding AXI interconnects.

What I think it automatically does, which it does not make the user aware of, is passing AXI burst information directly from master to slave when it does the “width conversion”, instead of actually doing a proper conversion of the AXI burst (ARSIZE, ARLEN, ARADDR).

For most use-cases this is not the behavior that you would want, basically making this “automatic feature” unusable.

I think this section in the platform designer user guide kind of hints at that:

https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/width-adaptation-and-data-packing-in-platform-designer

We believe it is passing the request as a “narrow AXI” request, which isn’t supported by the fabric NOC and/or NOC initiator/HBM.

To work around this, I think we could either:

- Update the DMAs to operate at 512b instead of 256b (would consume too many routing resources)

- Implement our own 256b to 512b converters (redundant with the automatically inserted, non-functioning converters. so wastes ALM resources)

- Update some of the NOC initiators for 256b instead of 512b (not fast enough, and we would lose the benefits of using the fabric NoC (available when doing 512b))

None of these work arounds are acceptable for us.

Can you please help us make the automatically inserted bus width converters function properly?

If we switch to Avalon bus would they work properly, and maintain single clock accesses to HBM?

Note: We are using Quartus Prime Pro 25.1.0