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Jed_Nextera_ASAP's avatar
Jed_Nextera_ASAP
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7 days ago

Agilex 7M HBM Bus Width Converter Failure

While testing an HBM DMA design we found our DMA read was seeing the data from the HBM, but words were missing.  We intended to read 36x 256-bit words.  We are seeing 18 words read and 18 words beyon...
Programmable Logic Device
ShengN_altera's avatar
ShengN_altera
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3 days ago

Hi,

Could you try interconnect width adaptor type with enable the Optimized converter (faster, higher area) https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/correcting-platform-designer-system-timing-issues

If that doesn't solve the problem, try AXI Bridge Intel FPGA IP https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/axi-bridge-intel-fpga-ip

With an AXI bridge, you can influence the placement of resource-intensive components, such as the width and burst adapters. Depending on its use, an AXI bridge may reduce throughput and concurrency, in return for higher fMAX and less logic.

 

If we switch to Avalon bus would they work properly, and maintain single clock accesses to HBM?        I think you can try this as well.