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Altera_Forum's avatar
Altera_Forum
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16 years ago

Pin assignment in Quartus II

Hi all,

After my design is added to the project if I tried to assign the pins automatically using compile Design option or I/O assignment analysis option available under compile design tool is giving a critical warning stating that "No exact pin location assignment for 29 pins of 49 total pins". This is happening for all my designs. Only Data pins are getting allocated every time i tried.

Although i can allocate them manually using pin planner, but I need the default or suggested pin allocations.

Kindly help me

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Forgot to mention the tool used. Quartus II

    --- Quote End ---

    Hi,

    it is not clear to me what you try to achieve ? Do you have a board with an FPGA and want to assign your design ports to certain FPGA pins ? Can you post your <>.qsf file ?

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I believe if you want to let Quartus II do the pin assignments for you, you don't have to go to pin assignment. Just compile the project and finish routing. It should be able to assign the pins for you randomly.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    No its not allocating the pins even I just compiled the design. Just beacause it is not allocating I choose pin planner. I want the allocation without pin planner involvement.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You can allocate the pins in the HDL

    in SystemVerilog do:

    module a(

    (* chip_pin = "A13" *) input wire LVDS_RX,

    (* chip_pin = "A14" *) output reg LVDS_TX);
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Laxmanv. I assume you want to compile your design and stop quartus from warning about assigned pin locations? Is this what your asking?

    Normally if your using a dev kit, do not let quartus do pin assigment. However if your on a new design, then just compile it and quartus fitter will assign pins. Then use back annote assignments command.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yeah, what you need to do is let Quartus II handle the random pin assignments. I believe it is the same for Xilinx ISE. Then after that, go to pin output file (in txt format) to view the pin report that is assigned by Quartus II

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    But I want the allocations in QSF. Lets take an example of Xilinx MIG. If we select any banks for user allocation then the pins get allocated in the selected banks by following pin allocation rules. If we didn't select any banks it 'll proceed with Default bank selections and outputs the UCF(user copnstraints file) with all pin alloctaions. I want the similar way here.

    Is there any option like that in IPtool bench or Quartus II?.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    But I want the allocations in QSF. Lets take an example of Xilinx MIG. If we select any banks for user allocation then the pins get allocated in the selected banks by following pin allocation rules. If we didn't select any banks it 'll proceed with Default bank selections and outputs the UCF(user copnstraints file) with all pin alloctaions. I want the similar way here.

    Is there any option like that in IPtool bench or Quartus II?.

    --- Quote End ---

    Hi,

    looks like that my post is missing.

    you can preserve the pin assignment choosen by Quartus. You have to back-annotade the assignment. You can do that in following way:

    Choose:

    Assignment -> Back-Annotate Assignments

    Stay with the default setting "Pin&device Assignment" and press ok.

    The assignments are now written into the QSF.

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for the reply, But how about if the Address pins are not allocated, i.e if it produces the warning message which I mentioned in previous post.