Parametric phase delay fpga quartus

Question

I want to generate multiple signals, and they must be phase shifted. The every phase would be calculated and have to be insert in automatically. I think about using parameters, but I don't now exactly how to do it. It is even possible?
Altera cyclone II

farabi · Answer

Hello,

You can use PLL to introduce phase shift delay in your signals.

link : https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/altera-phase-locked-loop-ip-core-user-guide.html

regards,

Farabi

tom16 · Answer

But I need signal in khz not Mhz. Is it any other way? It also can be some kind of delay.

agors5 · Answer

So divide it.Use PLL to generate MHz signal and dived it to khz signal.Use PLL dynamic phase shift to control kHz phase shift. Taaadaaaa.

tom16 · Answer

Yeah but I if you divide it by counter - any phase shift on MHz signal would be negligible kHz shift. I need it to be significant. Altpll_reconfig isn't available, if it is what you meant.

agors5 · Answer

PLL has user interface for on-the-fly phase shift control. You can change it without reconfiguration with 96ps steps min.
So divide c0 and C1 separatelly. Then you can change phase shift between then on the fly.

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Parametric phase delay fpga quartus

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