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Tom16's avatar
Tom16
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3 years ago

Parametric phase delay fpga quartus

I want to generate multiple signals, and they must be phase shifted. The every phase would be calculated and have to be insert in automatically. I think about using parameters, but I don't now exactly...
AGORS5's avatar
AGORS5
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3 years ago
So forget about PLL.
Use generated synchronus registers chain. Then you can define length as parametr.
Three will be always small time difference in output signal due to difference in routing. Definitelly below 5 ns im total.
Tom16's avatar
Tom16
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3 years ago
I will try it, thanks