Output delay constraints

Here is my understanding, hope it doesn't confuse you further:

system approach:

Output delay is interpreted as the tSU and -tH of external device as seen at fpga pins. The delay values can be worked out from tSU, tH of output device plus the effect of board delays:

Max : tSU + max data delay – min clk delay

Min : - tH + min data delay – max clk delay

However, in my opinion board delays let alone min/max board delay is theoretical rubbish...Can anybody measure it for sure ?

skew approach:

Use this method if device requires min skew or you just want to set your fpga timing irrespective of any device. However, if device has tSU/tH requirement then you must use system approach. It is not an alternative.

For edge aligned case:

Max : unit interval – skew

Min : skew

For centre aligned case:

Max = (unit interval / 2) - maximum skew value.

Min = maximum skew value - (1.5 * unit interval).

Hi, Thanks for your reply.

system approach:

>> max : tsu + max data delay – min clk delay

>> min : - th + min data delay – max clk delay

I understand the data delay and clk delay depends on trace length, if the length are same,then Max delay=Tsu, Min Delay=Th?

skew approach:

>>however, if device has tsu/th requirement then you must use system approach.

I think, still we can use skew approach. Any idea of what the below formulae tends to express?

Max = (unit interval / 2) - maximum skew value.

Min = maximum skew value - (1.5 * unit interval).

Skew value is the setup time in max and hold time in min?

if clock/data trace lengths are equal then you can ignore the board effect. In essence if they are not equal then tSU/tH as seen at fpga pins is modified.

You must note (minus) tH for min delay.

The equation is given by altera, see timequest resource centre/examples/centre aligned output delays

with regard to skew approach as alternative to system approach, I think it kills the whole idea of getting timing right. We must meet the external device timing. It is only good if by coincidence it gets it right !! or if the external device only requires min skew.

What is the skew value represented in the below equation?

Max = (unit interval / 2) - maximum skew value.

Min = maximum skew value - (1.5 * unit interval).

It is the skew of bus elements (difference of transition times that occur from bit to bit of output data bus).

You decide an affordable value for the fpga. You will be lucky if you get it or may be you get better than what ask for.

It is purely fpga parameter. It does not see the external device...

example 250 ps is commonly used by altera examples.

One obvious thing that TimeQuest documentation does not tell (possibly for commercial reasons) is this:

whether delay figures mean tSU or tH or skew or any other expression then at the end of the day the tool does not know or care about how you got it the figures. Nor is the tool ever so precise as to get your figures.

For outputs, you aim at getting clk to data delay from fpga optimum for external device... thats all