Output delay constraints

if clock/data trace lengths are equal then you can ignore the board effect. In essence if they are not equal then tSU/tH as seen at fpga pins is modified.

You must note (minus) tH for min delay.

The equation is given by altera, see timequest resource centre/examples/centre aligned output delays

with regard to skew approach as alternative to system approach, I think it kills the whole idea of getting timing right. We must meet the external device timing. It is only good if by coincidence it gets it right !! or if the external device only requires min skew.