Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorOutput delay constraints
Hi, I have center-aligned DDR output interface in my design. Output data is given through ALTDDIO_OUT driven by PLL clock output (0 deg) and the clock output is given by another PLL clock output ...
Altera_ForumHonored Contributor
Honored ContributorHi, Thanks for your reply.
system approach: >> max : tsu + max data delay – min clk delay>> min : - th + min data delay – max clk delay I understand the data delay and clk delay depends on trace length, if the length are same,then Max delay=Tsu, Min Delay=Th? skew approach: >>however, if device has tsu/th requirement then you must use system approach. I think, still we can use skew approach. Any idea of what the below formulae tends to express? Max = (unit interval / 2) - maximum skew value. Min = maximum skew value - (1.5 * unit interval). Skew value is the setup time in max and hold time in min?
