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Altera_Forum
Honored Contributor
Honored ContributorOutput delay constraints
Hi, I have center-aligned DDR output interface in my design. Output data is given through ALTDDIO_OUT driven by PLL clock output (0 deg) and the clock output is given by another PLL clock output ...
Altera_ForumHonored Contributor
Honored ContributorWhat is the skew value represented in the below equation?
Max = (unit interval / 2) - maximum skew value. Min = maximum skew value - (1.5 * unit interval).
