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Altera_Forum
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15 years ago

Output delay constraints

Hi, I have center-aligned DDR output interface in my design. Output data is given through ALTDDIO_OUT driven by PLL clock output (0 deg) and the clock output is given by another PLL clock output ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

It is the skew of bus elements (difference of transition times that occur from bit to bit of output data bus).

You decide an affordable value for the fpga. You will be lucky if you get it or may be you get better than what ask for.

It is purely fpga parameter. It does not see the external device...

example 250 ps is commonly used by altera examples.