Output delay constraints

Here is my understanding, hope it doesn't confuse you further:

system approach:

Output delay is interpreted as the tSU and -tH of external device as seen at fpga pins. The delay values can be worked out from tSU, tH of output device plus the effect of board delays:

Max : tSU + max data delay – min clk delay

Min : - tH + min data delay – max clk delay

However, in my opinion board delays let alone min/max board delay is theoretical rubbish...Can anybody measure it for sure ?

skew approach:

Use this method if device requires min skew or you just want to set your fpga timing irrespective of any device. However, if device has tSU/tH requirement then you must use system approach. It is not an alternative.

For edge aligned case:

Max : unit interval – skew

Min : skew

For centre aligned case:

Max = (unit interval / 2) - maximum skew value.

Min = maximum skew value - (1.5 * unit interval).