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Altera_Forum
Honored Contributor
Honored ContributorOutput delay constraints
Hi, I have center-aligned DDR output interface in my design. Output data is given through ALTDDIO_OUT driven by PLL clock output (0 deg) and the clock output is given by another PLL clock output ...
Altera_ForumHonored Contributor
Honored ContributorOne obvious thing that TimeQuest documentation does not tell (possibly for commercial reasons) is this:
whether delay figures mean tSU or tH or skew or any other expression then at the end of the day the tool does not know or care about how you got it the figures. Nor is the tool ever so precise as to get your figures. For outputs, you aim at getting clk to data delay from fpga optimum for external device... thats all
