On-Chip Memory Read/Write Issue

Okay! I think I got it! Thank you!

Do I need to mmap the second port of the sram as well? I only see a single base address for the sram.

But in the qsys I see two addresses. (Shared above)

Thanks

Hi Sheng,

The link that you shared only has the base address. I need to access the clken, write, writedata etc pins.

How do I access them?

Regards

Hi Sheng,

Thanks for sharing these links.

I am assuming the SDRAM controller is specifically made for the SDRAM. Can the DMA be used for it? Can the DMA Controller be used for the on-chip ram?

Thanks

Hi Sheng,

I read the documentation for the Quartus Prime 17.0 which didn't mention DMA controller compatible with Cyclone V. I compiled the design with the Quartus version 23.1 and I see some activity on signal tap from the DMA pins.

This is a question regarding the On-Chip Memory (RAM or ROM) Intel FPGA IP module. I have instantiated this module in the Qsys in the dual port mode and enabled "Initialize Memory Content". After loading this design on the FPGA I run a C code from the linux on the FPGA which tries to access the memory. Below is how the memory is connected to the HPS:

I am trying to mmap. What would be the base address for the on-chip memory FPGA ip? According to the HPS memory map, the ocram base address is 0xFFFF0000. I tried doing that but I get segmentation error.

The next I tried is 0xC0000000 since it is connected to the mai axi bus, and then add the offset address which is 0x08000000 (as shown in the qsys). I am able to read a constant value from this address. Would that be correct?

How to access the second port? Do I need to mmap it again?

Hello,

I was able to make the DMA controller work. The data from the FIFO is being sent to the SRAM.

I am now trying to figure out if I can increase the DMA transfer speed. I am sweeping signals from 1Hz to 5Khz. I can see signals till 1Khz decently, however, after that the data starts breaking and is distorted after 2KHz.

Thanks for your time and assistance!

Regards