Honored ContributorHi everyone,
I am working with a cyclone II and NIOS II development kit.I wanna enhance the performance of my ISR. I read that I could do that by placing the ISRs and teh stack in the fastest available memory (on chip memory for example). But how do I do thta? Should I, in SOPC Builder, put the reset vector of the CPU on my on-chip-memory? If yes, is that enough?? :confused: Thank you, éléa
Honored ContributorAs Nios II doesn't have vectored interrupts, it should be enough with putting "Exception Vector", not "Reset Vector", at on-chip memory. In Nios II IDE you can mark the option "Use separate exception stack" at system library properties.
Honored ContributorPlacing the exception vector in onchip memory will work in some cases. In some cases it will not work. You can explicitly assign code to reside in a specific memory section by using attributes in your C code. Refer the the "Memory Usage" chapter of the following section of the NIOS II literature:
http://www.altera.com/literature/hb/nios2/n2sw_nii52004.pdf JakeHonored ContributorThank you very much for your answer. I have tried to create an linker script with sections of code and the place where the system should put my exceptions (so on my on-chip memory) but the results were quite strange:
I tried to measure the response of an excitation of my system (in fact a generator of pulse is connected to a GPIO, when an IRQ is produce, the code writes on another GPIO and I measure the time between the excitation and the response of the system). The thing is that it took more time when the exceptions were on the on-chip memory than on the sdram (when I used my linker script ). Is it normal? What is more, when I simply put on System Library properties the exception memory on on chip memory, it took less time than with my linker script. So the results were: exceptions on on-chip without linker script < exceptions on sdram < exceptions on on-chip WITH linker file Is it normal?? ThanksHonored ContributorWhen you use a linker script to put some exceptions code at on-chip memory; you are considering just the ISR, not the exception vector. Don't forget that Nios II Exceptions are not vectored. The improvment in time response is given by an on-chip memory exception vector, not by putting interrupt service routines at on-chip memory.
