Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

on chip memory and ISR

Hi everyone, I am working with a cyclone II and NIOS II development kit.I wanna enhance the performance of my ISR. I read that I could do that by placing the ISRs and teh stack in the fastest avai...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

When you use a linker script to put some exceptions code at on-chip memory; you are considering just the ISR, not the exception vector. Don't forget that Nios II Exceptions are not vectored. The improvment in time response is given by an on-chip memory exception vector, not by putting interrupt service routines at on-chip memory.