Forum Discussion
Honored Contributorobject assigned a value but never read - does this effect synthesis?
Hello,
I have the following small module which is intended to store the value 0xFF in a register when a button is pressed.
module connector_test(button, txd);
input button;
output reg txd;
reg data;
always @(button) begin
if(button==1'b0) begin
txd <= 1'b0;
data <= 8'hFF;
end
else begin
txd <= 1'b1;
data <= 8'b0;
end
end
endmodule
15 Replies
Altera_ForumReal registers for which norpune works need a clock, generated e.g. by always @(posedge clk) block.
- Altera_Forum
Thanks for the reply
- Altera_Forum
Perhaps you're correct - could you elaborate a little more?
I understand that declaring something as reg doesn't mean that it will be synthesized as an actual sequential element. The synthesizer could very well turn it into combinational logic - but how do you know that its being interpreted as a group of combinational cells? Since it hasn't made it into the final circuit - I'm not sure how to know what the synthesizer has interpreted it as. Secondly, you said that you used real registers - what exactly was this implementation? A look at the experimental code you used would be helpful for this. Thanks again. -k - Altera_Forum
I notice a possible misunderstanding. "noprune" is said to preserve registers with no fanout. data isn't a register, it's a (group of) combinational logic cell(s).
I did my previous test with real registers, and they worked well. - Altera_Forum
Interesting, the Xilinx equivalent of noprune 'S' (for save) synthesizes correctly and uses 8 LUTS as indicated in the report. What's the solution to get this working in Quartus?
- Altera_Forum
You're suggesting that perhaps since no other resources are being occupied (other than the fan-out-less register I'm trying to keep) that the compiler may ignore the synthesis attributes?
Have you seen such behavior before? -k - Altera_Forum
With zero resource things may not be predictable.
Your design indeed is implemented as just wiring input button to output txd directly. I suggest you try a bit more logic to keep compiler happy. - Altera_Forum
@FvM - I'm checking for the synthesis of the register by simply looking at the compilation report giving statistics on the final design. It says that the total number of registers in the design is zero. I can confirm this by opening the RTL viewer - no registers - only ports.
@ashishkaps (http://www.alteraforum.com/forum/member.php?u=60151) - Yes, I've read through the article - and I've tried both versions of giving the attribute - neither worked. It seems odd, I'm not sure what the issue is? What version of Quartus are you running - could it be a bug? I'm using version 12.0 of Quartus II. +------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+-----------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Tue Sep 18 12:05:38 2012 ; ; Quartus II 32-bit Version ; 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition ; ; Revision Name ; connector_test ; ; Top-level Entity Name ; connector_test ; ; Family ; Cyclone III ; ; Total logic elements ; 0 ; ; Total combinational functions ; 0 ; ; Dedicated logic registers ; 0 ; ; Total registers ; 0 ; ; Total pins ; 2 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+-----------------------------------------------+ - Altera_Forum
Yes, the warning "reg assigned a value but never read" won't be supressed by the noprune attribute, IMHO pretty reasonable. The register however appears in the gate level net list and is counted in resource utilization.
- Altera_Forum
Check out this link
http://quartushelp.altera.com/11.1/mergedprojects/hdl/vlog/vlog_file_dir_noprune.htm It gives two ways to use the attribute. Plus one more way to give a switch through the .qsf file to preserve fanout free node. In my opinion use the attributes rather than switches. Coming to the warning i agree with FVM that the attribute will work and the warning will come even though the tool is preserving the registers, as you are not using your signal "data" anywhere in your module. Check the map.rpt and see whether your register has been preserved.
