object assigned a value but never read - does this effect synthesis?

Since the logic is not used, the synthesis tool removes it.

To force the tool to keep the logic, look at the synthesis directives in Quartus help, you want to use "noprune":

http://quartushelp.altera.com/12.0/mergedprojects/hdl/vlog/vlog_file_dir_noprune.htm

Cheers,

Dave

Thanks for the reply - that's enlightening!

Unfortunately, after adding the synthesis attribute, the register is still not synthesized.

Is there a setting in Quartus that needs to be enabled so that synthesis attributes are not ignored - or am I simply using this incorrectly?

The new code is below:

module connector_test(button, txd);
input button;
output reg txd;
reg  data /* synthesis syn_noprune */;
always @(button) begin
    if(button==1'b0) begin
        txd <= 1'b0;
        data <= 8'hFF;
    end
    else begin
        txd <= 1'b1;
        data <= 8'b0;
    end
    
end
endmodule

Here's what I've used:

    // ------------------------------------------------------------
    // SignalTap II counter
    // ------------------------------------------------------------
    //
`ifdef USE_SIGNALTAP
    logic  count /* synthesis noprune */;
    always_ff @ (posedge clkin, negedge pcie_perstN)
    if (~pcie_perstN)
        count <= '0;
    else
        count <= count + 1;
`endif

This preserves a counter that goes nowhere, which I can then probe with SignalTap ... which arguably means it goes somewhere ... however I needed to add this constraint so that Quartus would keep the counter so that I could probe it.

There are a few other synthesis attributes; keep, preserve, etc. Try a few :)

Cheers,

Dave

Yes, I've looked at the other available attributes - and the only other that looks like it might apply is preserve - sadly, this didn't seem to work either.

It looks like the noprune attribute is exactly what is needed in my case also, I'm not sure why it isn't responding to it.

Do you recall having to do anything before using the attributes - or they just "work"?

I also tried using type logic instead of reg as your have in your example - but this didn't change anything either.

Any other suggestions?

Thanks again!

-k

Check out this link

http://quartushelp.altera.com/11.1/mergedprojects/hdl/vlog/vlog_file_dir_noprune.htm

It gives two ways to use the attribute.

Plus one more way to give a switch through the .qsf file to preserve fanout free node.

In my opinion use the attributes rather than switches.

Coming to the warning i agree with FVM that the attribute will work and the warning will come even though the tool is preserving the registers, as you are not using your signal "data" anywhere in your module.

Check the map.rpt and see whether your register has been preserved.

@FvM - I'm checking for the synthesis of the register by simply looking at the compilation report giving statistics on the final design. It says that the total number of registers in the design is zero. I can confirm this by opening the RTL viewer - no registers - only ports.

@ashishkaps (http://www.alteraforum.com/forum/member.php?u=60151) - Yes, I've read through the article - and I've tried both versions of giving the attribute - neither worked.

It seems odd, I'm not sure what the issue is?

What version of Quartus are you running - could it be a bug?

I'm using version 12.0 of Quartus II.

+------------------------------------------------------------------------------------+

; Analysis & Synthesis Summary ;

+------------------------------------+-----------------------------------------------+

; Analysis & Synthesis Status ; Successful - Tue Sep 18 12:05:38 2012 ;

; Quartus II 32-bit Version ; 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition ;

; Revision Name ; connector_test ;

; Top-level Entity Name ; connector_test ;

; Family ; Cyclone III ;

; Total logic elements ; 0 ;

; Total combinational functions ; 0 ;

; Dedicated logic registers ; 0 ;

; Total registers ; 0 ;

; Total pins ; 2 ;

; Total virtual pins ; 0 ;

; Total memory bits ; 0 ;

; Embedded Multiplier 9-bit elements ; 0 ;

; Total PLLs ; 0 ;

+------------------------------------+-----------------------------------------------+

With zero resource things may not be predictable.

Your design indeed is implemented as just wiring input button to output txd directly. I suggest you try a bit more logic to keep compiler happy.

You're suggesting that perhaps since no other resources are being occupied (other than the fan-out-less register I'm trying to keep) that the compiler may ignore the synthesis attributes?

Have you seen such behavior before?

-k