nStatus unconnected on cyc1

How about reading the device handbook? Figure 13–16 jtag configuration of single cyclone fpga is exactly showing the minimal circuit requirements. Optional connections are discussed in the accompanying text.

P.S.: The JTAG signals are not named Di, Do, Dclk, by the way.

First of all thanks for the quick reply.

I already saw figure 13-19 which describes the connection. nevertheless, although nstatus need to be connected to 10KE pull up resistor, I have no problem to configure the FPGA without this connection.

So my question is:

Can I use it without nstatus connected to pull up ?

or

what are the condition that will allow me to pass on this connection?

thanks

P.S : JTAG names tDI, tDO, tCK, TMS

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I have no problem to configure the FPGA without this connection.

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Possibly. But do you know if it's by chance or by design (which would mean, that the device handbook is incorrect in this regard)? Who do you think can answer your question?

To be honest, I don't care. Generally, I would follow the manufacturers specification.

There may be special cases, where you need to know. E.g. you shipped a product and found a possible cause of failure (according to the manufacturers specifcation) later on. If you have reason to believe (or just hope), that the specification may be incorrect, you may want to find out the real behaviour. Your result may be still incorrect, but possibly sufficient for a decision about a return call for your products.

In addition, JTAG-only is a configuration scheme of rather limited purpose. For this reason, you won't find much users, that have tried the same.

Well,

I understand that even, by chance, it is working - you are suggesting not to work with this kind of configuration (nstatus is not connected).

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In addition, JTAG-only is a configuration scheme of rather limited purpose. For this reason, you won't find much users, that have tried the same.

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Jtag can perform FPGA programming and if it will be used for this purpose only (program FPGA via jtag each power up by a proccesor), I think it will be OK. Don't you ?

(ALTERA also gave the source code and documantation for programming FPGA using JTAG and its called "jrunner")

Maybe to program the FPGA with PS is better ? (but no SW to support in PS programming)

thanks,

Amir

Mostly embedded processors are using PS instead of JTAG for configuration because the protocol is simple. In my opinion, the interface is documented by Altera, there are also embedded software examples. But basically you are sending a binary bitstream using the PS specifcation in the hardware manual.

JTAG can work as well.

Thank you FvM for the answers.

I'll try to connect the nStatus pin, because there is no guarantee that it will work always in JTAG or PS mode (the specification are not talking about the option of leaving it unconnected)