Forum Discussion
Honored ContributornStatus can't go high
I have just finished my pcb of EP3C25F324, but it can't work
when I power on the board, all user IO pins stayed high, the nSTATUS remaid low, and nCONFIG statyed high. Is't the problem of POR? Or the power of VCCA,VCCINT,VCCIO have some problem? I used the JTAG an AS config way via the Figure 10-30 on cyclone3 device handbook,following is my scheme,and I connect VCCIO1 to the VCC3.3,and the others to the VCC2.5. http://1824.img.pp.sohu.com.cn/images/2009/6/17/9/26/122983f4b5dg214.jpg15 Replies
Altera_ForumSo are you able to program something into the EPCS flash? Are you able to program the part via JTAG?
Jake- Altera_Forum
thanks for your reply!
I can't program anything via JTAG,when I config the FPGA ,the quartus programmer said:can't access the JTAG(I use usb blaster). - Altera_Forum
Can you list what all of your voltage rails are connected to including VCCINT?
Jake - Altera_Forum
It's scheme of power, is this enough?
http://1834.img.pp.sohu.com.cn/images/2009/6/17/14/0/122995e0772g215.jpg - Altera_Forum
Since nSTATUS is stuck low it sounds like it could be a POR problem. Though I don't know of a POR problem with this specific device for Altera. But there are other reasons a device may not exit POR too, like voltage levels on supplies all must be above the POR trip points, control pins need to be tied or driven correctly, etc...
Debug techniques: I would put a scope on nSTATUS and trigger on a rising edge, single sequence (Single event trigger, one time trigger). Try varying trigger point voltage levels. Around 0.2 to 0.8V and look for a rising pulse then nSTATUS should drive low when entering POR, but should also release nSTATUS back high again after POR. Also list for us your voltage supplies and what they are powered to. Especially VCCIO of the banks that have configuration pins in them. I noticed the JTAG header is powered at 2.5V, the EPC is powered at 3.3V, what are the voltages of VCCIO for these banks? - Altera_Forum
thanks for your help,I will try the Debug techniques later.
as the scheme of powet above, I connect the VCCIO of bank1 to the 3.3V, I have doubt this, because the jtag pins and EPC pins are both in the bank1, but jtag is powered at 2.5V and EPC is powered at 3.3V. I followed the Figure 10-30 on cyclone3 device handbook to design the config scheme(Programming Serial Configuration Devices In-System Using the JTAG Interface). VCCIO of bank1: 3.3V VCCIO of other banks: 2.5V VCCINT:1.2V VCCA: 2.5V MSEL :0010 (1 to 2.5V) (you can see the detailed connection via the scheme above, maybe it's not clear enough, you can save it to your local coputer and then enlarge it) - Altera_Forum
Just following up to see if you managed to resolve the problem, need more help, moved on to other things, etc... ???
If you resolved it... what did you determine the root cause of the problem to be? What was your resolution? - Altera_Forum
Hi,
I have the same problem. My device is EP3C55F484. I'm using JTAG and SFL to programm my EPCS16. All VCCIOs are 3.3V, VCCINT = 1.2V, VCCD_PLLs are 1.2V and VCCA = 2.5V. JTAG is powered by VCCA, TDI and TMS are tied to VCCA via 1k, TCK is tied to GND via 1k. MSEL: 0010. When I power on my board nSTATUS stays low, nCONFIG stays high. I doublechecked all voltage levels and everythig was fine. I think that Cyclone can't exit POR but I don't understand why(( - Altera_Forum
I met the same problem with you: the nstatus can not go high and I can't configured the EP3C40 via JTAG neither.
So have anyone solved this problem? Maybe you can help me with your experience. Many thanks. - Altera_Forum
I have solved the JTAG problem. The reason is that VCCINT and VCCA were not powered correctly.
--- Quote Start --- I met the same problem with you: the nstatus can not go high and I can't configured the EP3C40 via JTAG neither. So have anyone solved this problem? Maybe you can help me with your experience. Many thanks. --- Quote End ---
