No logic elements although I have an output

The problem I got after removing for statement is that , I have a shared signal which is a 2D array. I assigned values to different cells in each process. But in compilation, Multiple constant assignent error is shown . My question is that , Isn't it possible to assign values to the same array in different processes if the places of assignment are different ?

This is the code if you may...

-- In process 1 :

if (clk' event and clk='1') then

Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5;

end if;

-- In process 2 :

if (clk' event and clk='1') then

Bufftemp(2*j,2*i)<= Im(2*j,2*i) - 5;

end if;

Error : Error (10028): Can't resolve multiple constant drivers for net "Bufftemp[0][0][9]"

--- Quote Start ---

I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation.

1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware.

2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part.

3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design?

Have you tried to simulate this in a simulator? like modelsim?

--- Quote End ---

Dear Moderator ,

I will consider all your points , Actually I read books for Pedroni and Pong about VHDL programming , I know I still have a lot to learn since I unconsciously back to sequential programming I used to utilize. About your notes, I will move the counters , this point I got it clearly.

-- About signals , I will use them and hopefully you guide me to certain book that I can have better understanding.

--Modelsim is not work often with my designs ! I am using Quartus !

Finally about the latency , I am thinking of unnecessary statement of signal assignment , but this will costs 1 clock cycle .. where is the other two?

Dear, I am really appreciate your help and reply , I have designed an algorithm but I know I am unable to implement it well, as a consequence , each note you give will raise the implementation a lot. And I am ready to read any book you suggest

Thanks again.

I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation.

1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware.

2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part.

3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design?

Have you tried to simulate this in a simulator? like modelsim?

Thank you very much Tricky and FvM. I am really appreciate your instant help. I figured out a solution to read one element each clock cycle as listed as I see it best solution

Process (clk)

variable i,j:integer range 0 to 7:=0;

begin

i:=i+1;

if i=7 then

i:=0;

j:=j+1;

end if;

if (clk' event and clk='1') then

Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5;

Buffsig<=Bufftemp(i,j);

OutResult<=Buffsig;

end if;

end process;