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Altera_Forum
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8 years ago

No logic elements although I have an output

Hello Please guide me why I don't see any logic element for the current code : LIBRARY ieee; USE ieee.std_logic_1164.all; Use ieee.numeric_std.all; USE work.my_data_types.all; -- to def...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thank you very much Tricky and FvM. I am really appreciate your instant help. I figured out a solution to read one element each clock cycle as listed as I see it best solution

Process (clk)

variable i,j:integer range 0 to 7:=0;

begin

i:=i+1;

if i=7 then

i:=0;

j:=j+1;

end if;

if (clk' event and clk='1') then

Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5;

Buffsig<=Bufftemp(i,j);

OutResult<=Buffsig;

end if;

end process;