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Altera_Forum
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8 years ago

No logic elements although I have an output

Hello Please guide me why I don't see any logic element for the current code : LIBRARY ieee; USE ieee.std_logic_1164.all; Use ieee.numeric_std.all; USE work.my_data_types.all; -- to def...
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Altera_Forum
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8 years ago

This will because buffsig is a constant. i and j are always 0 when assigning buffsig. And all buffsig values are assigned from a constant. So hence the design is reduced to a constant driver.