No logic elements although I have an output

I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation.

1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware.

2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part.

3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design?

Have you tried to simulate this in a simulator? like modelsim?