nios ii flash programming error

I think you have to set the proper offset for the flash. It is 0x20000.

And also check whether you reset address in the SOPC builder system (cpu configuration) points to your flash.

I have checked it,but when I run Auto-Assign-Base Address,the offset for flash will be set as 0x200000 and end address 0x3fffff.

And I have also checked that my reset address in the SOPC builder system points to my flash!

I think the information when I program show that the nios(cpu) has found the flash device!

Obviously the NIOS isn't able to program the flash.

Either:

1 - The interface to the flash is bad (like incorrect connections, pin assignments, not meeting timing, bad timing parameters etc.)

2 - The flash is write protected.

3 - The flash is corrupt.

Jake

#!/bin/sh

#

# This file was automatically generated by the Nios II IDE Flash Programmer.

#

# It will be overwritten when the flash programmer options change.

#

cd D:/NIOS_II/SRAM_FLASH/SopcLed/hello_world_small_0/Release

# Creating .flash file for the project

"$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00200000 --end=0x3fffff --reset=0x48000

0 --input="hello_world_small_0.elf" --output="cfi_flash.flash" --boot="E:/altera

/80/ip/nios2_ip/altera_nios2/boot_loader_cfi.srec"

# Programming flash with the project

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00200000 --instance=0 "cfi

_flash.flash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

: Checksumming existing contents

00000000 : Reading existing contents

Checksummed/read 16kB in 0.4s

00000000 ( 0%): Erasing

Erased 16kB in 0.2s (80.0kB/s)

00000000 ( 0%): Programming

Programmed 1KB +15KB in 0.3s (53.3KB/s)

Device contents checksummed OK

Leaving target processor paused

This means flash program OK?

Sure looks like it.

Oh I just remembered something. What flash device are you using. I know starting with version 7.1, the flash programmer started having problems with some Intel flash parts. Are you perhaps using a J3v.D Intel flash part?

Jake

No,Because I test it with one project ,it shows us the information :

cd D:/NIOS_II/SRAM_FLASH/SopcLed/hello_world_small_0/Release

# Creating .flash file for the project

"$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00200000 --end=0x3fffff --reset=0x48000

0 --input="hello_world_small_0.elf" --output="cfi_flash.flash" --boot="E:/altera

/80/ip/nios2_ip/altera_nios2/boot_loader_cfi.srec"

# Programming flash with the project

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00200000 --instance=0 "cfi

_flash.flash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

: Checksumming existing contents

00000000 : Reading existing contents

Checksummed/read 16kB in 0.4s

00000000 ( 0%): Erasing

Erased 16kB in 0.2s (80.0kB/s)

00000000 ( 0%): Programming

Programmed 1KB +15KB in 0.3s (53.3KB/s)

Device contents checksummed OK

Leaving target processor paused

//END

But when I use other project build by myself,it shows information like:

#!/bin/sh

#

# This file was automatically generated by the Nios II IDE Flash Programmer.

#

# It will be overwritten when the flash programmer options change.

#

cd E:/altera/80/workplace/RA8835/hello_world_1/Debug

# Creating .flash file for the project

"$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00200000 --end=0x3fffff --reset=0x20000

0 --input="hello_world_1.elf" --output="cfi_flash.flash" --boot="E:/altera/80/ip

/nios2_ip/altera_nios2/boot_loader_cfi.srec"

# Programming flash with the project

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00200000 --sidp=0x000010b0

--id=148608136 --timestamp=1252506938 --instance=0 "cfi_flash.flash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

Reading System ID at address 0x000010B0: verified

: Checksumming existing contents

00000000 : Reading existing contents

00004000 : Reading existing contents

00006000 : Reading existing contents

Checksummed/read 5kB in 0.1s

00000000 ( 0%): Erasing

00004000 (50%): Erasing

00006000 (75%): Erasing

Erased 32kB in 0.7s (45.7kB/s)

00000000 ( 0%): Programming

00004000 (50%): Programming

00006000 (75%): Programming

Programmed 28KB +4KB in 0.5s (64.0KB/s)

Verify failed at offset 0

Verify failed at offset 4000

Verify failed at offset 6000

Leaving target processor paused

//END

Shenhuan,

Maybe I explain this incorrectly, but I meant flash offset - Offset within the flash memory device where the FPGA configuration is to be programmed, not the base adderess of the Flash in the SOPC builder system. The offset is the relative address within the memory device where the configuration image is located. it is done in the flash programmer dialog window of the NiosII EDS or in the command line it is for example:

sof2flash --activeparallel --offset=0x20000 --input=niosII_lab.sof --output=hardware_image.flash

So you will have

# Creating .flash file for the FPGA configuration

"$SOPC_KIT_NIOS2/bin/sof2flash" --offset=0x20000 --input="C:/Trainings/nios_II_lab/niosII_lab.sof" --output="niosII_lab.flash

"

Info: *******************************************************************

Info: Running Quartus II Convert_programming_file

Info: Command: quartus_cpf --no_banner --convert

# Programming flash with the FPGA configuration

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x01000000 --sidp=0x02401098

--id=43463617 --timestamp=1248819551 --instance=0 "niosII_lab.flash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

Reading System ID at address 0x02401098: verified

: Checksumming existing contents

etc

this specifies hardware-image region of the flash memory.

Maybe this is not your case, but its worth to try to play with it. What offset are you specifying now?

uilka_b,

Thanks for your explanation.

I know the offset means you told,but I am programming *.elf to flash not FPGA configuration file,so my flash base address is 0x200000.

I set the Nios II Processor in the sopc_builder system like this:

Reset Vector: Memory:cfi_flash Offset:0x0 (Do you mean this place should be set as 0x2000??)

Exception Vector: Memory: sram Offset:ox20

//end

shenhuan:)

I thought you program both sof and elf to flash.

So I meant offset to specify hardware image region in the flash memory.

not addressing in the SOPC builder system.

Please describe step-by-step how you run your project in the board and how you configure your flash.