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Altera_Forum
Honored Contributor
16 years agouilka_b,
Thanks for your explanation. I know the offset means you told,but I am programming *.elf to flash not FPGA configuration file,so my flash base address is 0x200000. I set the Nios II Processor in the sopc_builder system like this: Reset Vector: Memory:cfi_flash Offset:0x0 (Do you mean this place should be set as 0x2000??) Exception Vector: Memory: sram Offset:ox20 //end shenhuan:)