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Altera_Forum
Honored Contributor
16 years agoShenhuan,
Maybe I explain this incorrectly, but I meant flash offset - Offset within the flash memory device where the FPGA configuration is to be programmed, not the base adderess of the Flash in the SOPC builder system. The offset is the relative address within the memory device where the configuration image is located. it is done in the flash programmer dialog window of the NiosII EDS or in the command line it is for example: sof2flash --activeparallel --offset=0x20000 --input=niosII_lab.sof --output=hardware_image.flash So you will have # Creating .flash file for the FPGA configuration "$SOPC_KIT_NIOS2/bin/sof2flash" --offset=0x20000 --input="C:/Trainings/nios_II_lab/niosII_lab.sof" --output="niosII_lab.flash " Info: ******************************************************************* Info: Running Quartus II Convert_programming_file Info: Command: quartus_cpf --no_banner --convert # Programming flash with the FPGA configuration "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x01000000 --sidp=0x02401098 --id=43463617 --timestamp=1248819551 --instance=0 "niosII_lab.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x02401098: verified : Checksumming existing contents etc this specifies hardware-image region of the flash memory. Maybe this is not your case, but its worth to try to play with it. What offset are you specifying now?