Forum Discussion
Honored ContributorNIOS II and Cyclone III Remote Update
Have spent several days now searching and reading and think I am nearly there... but not quite. I am using the NIOS II core with SOPC builder. I use Quartus II for the FPGA image. This is a project I have inherited which kept the FPGA image in a ECPS64 and the software image in CFI. I have combined the two and keep them in the EPCS64. Works OK. I have been trying to get the remote update controller to work. I have put it into the core via SOPC and can read and write its registers via NIOS. I can also make it do a reconfig but it always seems to use the factory image. Has any one got a working example using the Cyclone III and NIOS II?
I use the following to read 2 of the registers... ParamValue = IORD( REMOTE_UPDATE_CYCLONEIII_0_BASE, 0x4); ParamValue = IORD( REMOTE_UPDATE_CYCLONEIII_0_BASE, 0x0); After power on both registers read 0. After reconfig command, register 0 = 1 and register 4 = 8 Any ideas please? Brain is starting to hurt!69 Replies
Altera_ForumThe remote update register addressing is a bit tricky; it maps to 2 ports of remote update megafunction: param and read_source.
param is mapped to address bits 0-2 , while read_source is mapped to bits 3-4. Then address 0x04 refers to param 100 (boot address) and read_source 00 (current status) Address 0x0C refers again to param 100 (boot address) but read_source 01 (past status, before reconfiguration) Moreover, the boot address format is different between writes and reads: 22bits for writes and 24bits for reads. The values you read are correct up to the last 4 bits, which instead seem somehow random. Are you sure everything is properly connected? If your Nios runs at a frequency different from 25MHz you should have a clock crossing bridge between data master and remote update MM slave. If everything looks ok, try reading the register twice and check if you get the same value. If not, you definitely have a problem with connection or timing.- Altera_Forum
Indeed my Nios processor runs at a frequency of 80 MHz cpu_clk, I have a clock bridge with a frequency of 9,1 MHz and a frequency of 25 MHz for
the remote update MM slave, do I have to change the clock frequency of the remote update MM slave to correspond with the frequency of the clock bridge ? otherwise everything is well connected ! - Altera_Forum
Apparently I've a problem of CRC error when I try
to reconfig trig ! - Altera_Forum
IOWR(RU_BASE_B, 0x20, 0X1) does it work really ?
- Altera_Forum
OK for read the boot address I've got my first FPGA image now, so this point is Ok !
- Altera_Forum--- Quote Start --- Indeed my Nios processor runs at a frequency of 80 MHz cpu_clk, I have a clock bridge with a frequency of 9,1 MHz and a frequency of 25 MHz for the remote update MM slave, do I have to change the clock frequency of the remote update MM slave to correspond with the frequency of the clock bridge ? otherwise everything is well connected ! --- Quote End --- The purpose of the clock bridge is to interface two buses running at different clock rates, say clk1 for port s1 and clk2 for port s2. Then all devices on slave port side should have the same clk1 clock; similarly all devices on master port should use clk2. In your case, what's the point of using the clock bridge if you are still using a mismatched clock frequency after the bridge? The problems you have in reading/writing remote update core can be definitely due to this mismatch. Don't you have any warning from sopc builder?
- Altera_Forum
Warning: cpu: Custom Instruction components can be edited through the Component Editor.
Warning: cpu: Disabling the assign CPUID control register value manually will no longer auto-assigns unique control register value. This option will always be turned on with default value set to 0. That's the warnings I have. - Altera_Forum
What you're saying is that my two slaves ls_hdlc and remote_update_cycloneiii should have the same value of clock example ls_hdlc_clk, but the
master ls_hdlc_clock_bridge, I don't understand what you mean like value of clock ? - Altera_Forum
In reality I've the error Nconfig actived, don't if you know how to solve it cris72 ?
- Altera_Forum--- Quote Start --- What you're saying is that my two slaves ls_hdlc and remote_update_cycloneiii should have the same value of clock example ls_hdlc_clk, but the master ls_hdlc_clock_bridge, I don't understand what you mean like value of clock ? --- Quote End --- You should use ls_hdlc_clk for remote_update component, too. If you want to use slow_clock connect remote_update to the slow_clock_bridge master port. What's the problem? This is straightforward! You already have bridges to separate clock domains. What's the point in connecting remote_update slow_clock to different clock domain??? --- Quote Start --- In reality I've the error Nconfig actived --- Quote End --- nConfig is a FPGA input which is used to reset and trigger a reconfiguration! It's indeed controlled by an external component, then it CAN NOT signal any error.
