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What you're saying is that my two slaves ls_hdlc and remote_update_cycloneiii should have the same value of clock example ls_hdlc_clk, but the
master ls_hdlc_clock_bridge, I don't understand what you mean like value of clock ?
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You should use ls_hdlc_clk for remote_update component, too. If you want to use slow_clock connect remote_update to the slow_clock_bridge master port.
What's the problem? This is straightforward!
You already have bridges to separate clock domains. What's the point in connecting remote_update slow_clock to different clock domain???
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In reality I've the error Nconfig actived
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nConfig is a FPGA input which is used to reset and trigger a reconfiguration! It's indeed controlled by an external component, then it CAN NOT signal any error.
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