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Honored Contributor
Honored ContributorNIOS II and Cyclone III Remote Update
Have spent several days now searching and reading and think I am nearly there... but not quite. I am using the NIOS II core with SOPC builder. I use Quartus II for the FPGA image. This is a projec...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Indeed my Nios processor runs at a frequency of 80 MHz cpu_clk, I have a clock bridge with a frequency of 9,1 MHz and a frequency of 25 MHz for the remote update MM slave, do I have to change the clock frequency of the remote update MM slave to correspond with the frequency of the clock bridge ? otherwise everything is well connected ! --- Quote End --- The purpose of the clock bridge is to interface two buses running at different clock rates, say clk1 for port s1 and clk2 for port s2. Then all devices on slave port side should have the same clk1 clock; similarly all devices on master port should use clk2. In your case, what's the point of using the clock bridge if you are still using a mismatched clock frequency after the bridge? The problems you have in reading/writing remote update core can be definitely due to this mismatch. Don't you have any warning from sopc builder?
