Negative slack of Setup found by TimeQuest

Question

Hi everyone,

I use "altlvds_tx" (data rate = 300 Mbps, deser factor = 8, tx_coreclock = 37.5 MHz) in my project.

Also I have my VHDL module "FSM_Tx_Transport" servicing altlvds_tx.

The task of "FSM_Tx_Transport" is very simple, it only puts next byte to transmit on tx_in[7..0] of "altlvds_tx" every rising edge of tx_coreclock.

Main clock of "FSM_Tx_Transport" is 300 MHz.

After compiling I see some problems in TimeQuest report (only for Slow models while Fast model is fine).

Namely, there are some paths (within FSM_Tx_Transport) with negative slack of Setup.

Launch clock and latch clock of these paths are the same generated by PLL.

Here is an example of bad path from TimeQuest report:

Slack: -3.721

From node: FSM_Tx_Transport:inst1|counter[2]

To node: FSM_Tx_Transport:inst1|Tx_Out[6]

Lauch clock: inst8|altpll_component|auto_generated|pll1|clk[1]

Latch clock: inst8|altpll_component|auto_generated|pll1|clk[1]

Relationship: 3.333

Clock skew: -0.080

Data delay: 6.975

I examined relative location of both nodes in ChipPlanner. They are placed very close to each other.

How can I tune up my project to cancel negative slacks ?

Source code is attached.

Thank you.

https://www.alteraforum.com/forum/attachment.php?attachmentid=5167

altera_forum · Answer

In general, please write out a more detailed timing report and attach that instead. (Most people followers probably don't want to compile a project, but reading a single report file is pretty quick). Something like the following:

report_timing -to_clock { inst8|altpll_component|auto_generated|pll1|clk[1] } -setup -npaths 10 -detail full_path -panel_name {Setup: inst8|altpll_component|auto_generated|pll1|clk[1]} -file "TQ_failing_paths.txt"

Anyway, the critical path goes through 9 LUTs. That's probably way too much logic to run at 300MHz in the slowest Cyclone III family. The placement looks great, as there's only one LAB hop. Do you think the logic should be shorter than that?

altera_forum · Answer

Detailed timing reports (worst-case timing paths of all models) are attached.

--- Quote Start ---

Do you think the logic should be shorter than that?

--- Quote End ---

I think the code of "FSM_Tx_Transport" is compact to service of altlvds_tx. But I may be wrong.

300 MHz is minimal frequency to deal properly with tx_coreclock (37.5 MHz).

--- Quote Start ---

That's probably way too much logic to run at 300MHz in the slowest Cyclone III family.

--- Quote End ---

Do you think it's impossible to use slow Cyclone III for this task ?

What is the sense for Altera to announce possibility of 640 Mbps for LVDS in Cycone III ?

altera_forum · Answer

You can take a look in the Quartus options.

There are a lot of options to improve timing! Take a look at tools->advisors->timing_optimizations

P.S:

I don't think it is possible to use 300mhz in Cyclone III.

altera_forum · Answer

--- Quote Start ---  I don't think it is possible to use 300mhz in Cyclone III  --- Quote End ---   Cyclone III handbook states that core performance of EP3C16 (C8) is 402 MHz.

altera_forum · Answer

Core performance is theoretical. Sometimes DSP designs can run close to that fast because they literally pipeline between almost every level of logic, but 9 levels of logic won't run that fast. I didn't see if any failing paths were in the LVDS block, but the top failing paths were from the RTL. Can you pipeline it.

300MHz is do-able for some stuff, but it's not easy. (Heck, lots of Stratix designs don't run that fast.)

FYI, I just looked at a design that won't run at 20MHz in Arria II, which seems wrong at first glance. I looked and the critical path has over 400 levels of logic. So it varies...

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Negative slack of Setup found by TimeQuest

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