Honored Contributor
Honored ContributorDetailed timing reports (worst-case timing paths of all models) are attached.
--- Quote Start --- Do you think the logic should be shorter than that? --- Quote End --- I think the code of "FSM_Tx_Transport" is compact to service of altlvds_tx. But I may be wrong. 300 MHz is minimal frequency to deal properly with tx_coreclock (37.5 MHz). --- Quote Start --- That's probably way too much logic to run at 300MHz in the slowest Cyclone III family. --- Quote End --- Do you think it's impossible to use slow Cyclone III for this task ? What is the sense for Altera to announce possibility of 640 Mbps for LVDS in Cycone III ?
