Hierarchy | Input | Constant Input | Unused Input | Floating Input | Output | Constant Output | Unused Output | Floating Output | Bidir | Constant Bidir | Unused Bidir | Input only Bidir | Output only Bidir
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inst8|altpll_component|auto_generated | 2 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst8 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst | 52 | 2 | 0 | 2 | 51 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
inst1 | 52 | 1 | 0 | 1 | 10 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|shift_reg24 | 7 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|shift_reg23 | 7 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|outclk_shift | 11 | 9 | 0 | 9 | 1 | 9 | 9 | 9 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|cntr2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|cntr13 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|cmpr9 | 4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|cmpr20 | 4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|cmpr10 | 4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|outclock_ddio | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated|ddio_out | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst2|altlvds_tx_component|auto_generated | 9 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
inst2 | 9 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0