1) В проекте есть VHDL-модуль, работающий на частоте 300 МГц.
I use altlvds_tx (data rate = 300 Mbps, deser factor = 8, tx_coreclock = 37.5 MHz) in my project.
Also I have my VHDL module FSM_Tx_Transport servicing altlvds_tx. 
FSM_Tx_Transport puts next byte to transmit on tx_in[7..0] of altlvds_tx every rising edge of tx_coreclock.
Main clock of FSM_Tx_Transport is 300 MHz.

2) После компиляции проекта, TimeQuest выявил ряд путей (в рамках этого модуля) у которых имеется отрицательный slack 
у параметра setup.
After compiling I see some problems in TimeQuest report (only for Slow models while Fast model is fine in TimeQuest). 
Namely, there are some paths (within FSM_Tx_Transport) with negative slack of setup. 
Launch clock and latch clock of these paths are the same generated by PLL.

Here is an example:
Slack: -3.721
From node: FSM_Tx_Transport:inst1|counter[2]
To node: FSM_Tx_Transport:inst1|Tx_Out[6]
Lauch clock: inst8|altpll_component|auto_generated|pll1|clk[1]
Latch clock: inst8|altpll_component|auto_generated|pll1|clk[1]
Relationship: 3.333
Clock skew: -0.080
Data delay: 6.975

I examined relative location of both nodes in ChipPlanner. They are placed very close to each other.

3) Не вижу смысла в способности LVDS работать на скорости 840 Мбит/с (судя по datasheet), когда обслуживающая его логика уже
не работоспособна при тактовой частоте 300 МГц (deserialization factor = 8).

How can I tune up my project to cancel negative slacks ?
Source code is attached.