Negative slack of Setup found by TimeQuest

In general, please write out a more detailed timing report and attach that instead. (Most people followers probably don't want to compile a project, but reading a single report file is pretty quick). Something like the following:

report_timing -to_clock { inst8|altpll_component|auto_generated|pll1|clk[1] } -setup -npaths 10 -detail full_path -panel_name {Setup: inst8|altpll_component|auto_generated|pll1|clk[1]} -file "TQ_failing_paths.txt"

Anyway, the critical path goes through 9 LUTs. That's probably way too much logic to run at 300MHz in the slowest Cyclone III family. The placement looks great, as there's only one LAB hop. Do you think the logic should be shorter than that?