Forum Discussion
Altera_Forum
Honored Contributor
14 years agoNegative slack of Setup found by TimeQuest
Hi everyone, I use "altlvds_tx" (data rate = 300 Mbps, deser factor = 8, tx_coreclock = 37.5 MHz) in my project. Also I have my VHDL module "FSM_Tx_Transport" servicing altlvds_tx. The task o...
Altera_Forum
Honored Contributor
14 years agoNow I'm looking at "Timing Optimization Advisor".
It recommends the use of global clocks. But Current Global Settings are: Global Signal = Not Set (Recommended: Global Clock). It's surprise because I suppose the declaration of clocks in .sdc file (I did it with create_clock and derive_pll_clocks commands) makes them global without need of making assignmets in Assignment Editor. Where is the truth ? Thank you.