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Altera_Forum
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14 years ago

Negative slack of Setup found by TimeQuest

Hi everyone, I use "altlvds_tx" (data rate = 300 Mbps, deser factor = 8, tx_coreclock = 37.5 MHz) in my project. Also I have my VHDL module "FSM_Tx_Transport" servicing altlvds_tx. The task o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Look in the fitter report -> Resource Section -> Global Signals and see if your clock is on a global. Must likely it is. The .sdc does not make this happen, but the Fitter Settings -> More Settings -> Auto Global Clock Promotion, which defaults to on.

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Yes, Fitter report shows that all of the clocks are global, although there are no special assignments in Assignment Editor.

Your idea about pipelined logic is very interesting, I'll try it.

Thank you.