Forum Discussion
Honored ContributorNCO help...
Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i've been using to is the NCO megafunction. when i set the NCO to have a magnitude of 16 bits i get severe distortion and loss of precision, i cant change the NCO to have a smaller number of bits or i get a bit mismatch, and i cant reduce the number of bits of the filter because i get distortion and loss of precision again. i'm using simulink and fixed point advisor in simulink to design this filter....
Can anyone please help..? not sure if there is another way to test the filter with a more dynamic signal. or if anyone is familiar with simulink how i can optimize my design.36 Replies
Altera_ForumYeah there is a realizemdl function that generates them into simulink blocks, then from simulink i use the fixed point advisor tool to convert from floating point to fixed point, and then i use the HDL coder to generate HDL code. yes i do agree thats y ive been so lost i feel like ive been mislead and wasted a lot of time.
- Altera_Forum
Fair enough. But do you use the functions to generate the code or the simulink blocks. Put in other words, Does the blocks named LOwPassFilter ...etc do the rate transitions. In that case you don't need these transitions duplicated. It is a habit of diagrams makers to mislead when describing functionality !
- Altera_Forum
My apologies, the matlab function mfilt.firdecim and mfilt.firinterp already down sample and up sample. I put the transition blocks there because I want sure if it was necessary.
- Altera_Forum--- Quote Start --- No the blocks are in the right order, if you look at the link you see they are the same as the simulink model i posted. --- Quote End --- No that is not right. The link diagran puts H0 filter followed by down 2, your model puts rate transition then LOwPassFilter. Am I looking at the wrong link. Moreover it defies theory to put rate transition before decimating filter. For DSPBuilder you will choose blocks of decimator/interpolator and connect them. You choose your coeffs as well which might well be same as your or scaled for unity gain. The rate conversion is implied in the filter itself. Once done then you run DSPBuilder to generate code and testbench.
- Altera_Forum
No the blocks are in the right order, if you look at the link you see they are the same as the simulink model i posted. at this point i'm looking to do whatever it takes to make this work. i didn't know DSPbuilder was the industry standard. maybe i'll have better luck with that. how would i get this code into DSPbuilder, maybe then we'll be easier for us to be on the same page.
N = 99; [H0,H1,G0,G1] = firpr2chfb(N,.45); % Analysis filters (decimators). Hlp = mfilt.firdecim(2,H0); Hhp = mfilt.firdecim(2,H1); % Synthesis filters (interpolators). Glp = mfilt.firinterp(2,G0); Ghp = mfilt.firinterp(2,G1); - Altera_Forum
I am not sure about simulink generated code. I use DSPBuilder which is based on simulink blocks but specific blocks for target devices (altera or xilinx). DSPBuilder works but simulink is not used in the industry to generate code since there is DSPBuilder ...etc.
Now the question is why the order of blocks is not right. The second issue is that of NCO which was first title posted If you suspect NCO then you can rule that out by either rescaling your FIR coeffs or you can use random data or even just one impulse (1,0,0,0..etc) at required level, pass it through model then through hardware and see the difference. At the moment you will be checking model Versus hardware so if the model is wrong functionally it will not be relevant, you only want to check model against implementation. Once done then you start to question if model is correct. You are saying that simulation works ?? how could it be if the blocks are in the wrong order... I think you need to explain your setup and results further. - Altera_Forum
No i'm not writing my code. the QMF from the link i posted is what i'm trying to implement on the FPGA. After completing the tutorial from the link i used a tool to called simulink to convert to fixed point and generate HDL. thats what i've be trying to do the whole time. the simulations from simulink looks fine but when i try on the FPGA everything goes bad.
- Altera_Forum
I am a bit lost now. Do you write code or does Matlab generate it. If Matlab then who decided the blocks above since you said you decided the analysis fir and reconstruction fir. Whoever put the blocks they are not in the right order.
The idea of QMF is to split up signal into two independent branches, one for low frequency content and the other for high frequency content. Then each branch can be processed at half sampling rate and once done the signal is reconstructed by upsampling then adding both branches. The key to split point is the decimation to half Fs. The key to recombine point is interpolation back to Fs. The general rule for decimation is apply filter then decimate. The rule for interpolation is add zeros then filter. If you reverse the order e.g. decimate to Fs/2 then filter it is not going to work due to sampling violation of high frequencies at Fs/2. Similarly if you interpolate by a filter then add zeros (or else add what?) then it is meaningless. - Altera_Forum--- Quote Start --- But the link you provided shows rate transitions located correctly. Remember Matlab will help you model the design for testing. The actual implementation is up to your work (unless your tool generates design). --- Quote End --- It does that's why i'm still wondering why it's not working...not even sure where the fault is anymore. its either the fact that the NCO is connected incorrectly or the fault is with the way the tool generates the HDL code.
- Altera_Forum
But the link you provided shows rate transitions located correctly.
Remember Matlab will help you model the design for testing. The actual implementation is up to your work (unless your tool generates design).
